The present invention relates to a process for etching substrates, and in particular, for etching dielectric layers on semiconductor substrates.
In integrated circuit fabrication, it is often desirable to etch features in an electrically insulative dielectric layer 10 on a substrate 11, as schematically illustrated in FIG. 1a. The dielectric layers 10 include for example, silicon dioxide, undoped silicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Si.sub.3 N.sub.4, and silicon dioxide glass deposited from tetraethylorthosilane (TEOS). The dielectric layers 10 are typically used to electrically isolate devices formed on a semiconductor substrate 11, such as MOS gates formed in polysilicon underlayers 12; and can also be used to electrically isolate metal interconnect lines (typically aluminum/silicon/copper alloys) that are used to electrically connect the devices formed on the substrate (not shown).
In the etching process, a layer of photoresist is applied on the dielectric layer 10, and the photoresist layer is patterned using conventional photolithographic methods to form a patterned resist layer 14. Thereafter, conventional etching processes are used to etch features 15, such as contact holes or vias, through the exposed portions of the patterned resist layer 14. It is desirable for the dielectric etching process to provide etching selectivity ratios of greater than 10:1 with respect to the resist layer 14, and to provide etching uniformity across the substrate of less than 10%. The etching selectivity ratio is the ratio of the dielectric etch rate to the resist, or underlayer, etch rate. Etching uniformity is typically a statistical measure of the variation in size and depth of the etched features 15, across the substrate surface. After the etching process, the etched features 15 are filled with electrically conductive material 16 to form electrically conductive plugs or interconnects, which interconnect devices formed on the substrate, or interconnect lower levels of metal interconnect lines to upper levels of metal interconnect lines.
Modern VLSI and LSI integrated circuits often require etched features 15 having a particular predefined shape and/or cross-sectional profile. The desired shape and cross-sectional profile of the feature 15 can vary with the type of dielectric layer 14 that is etched, and the nature of subsequent deposition processes performed on the substrate 10. For example, in etching silicon dioxide glass deposited from tetraethylorthosilane (TEOS) it is often desirable to etch features 15 having an open-cup shape, as illustrated in FIG. 2b; and for etching BPSG glass, it is desirable to etch features 15 having a "wine-glass" profile, as illustrated in FIG. 2c. Both the cup and wineglass shaped profiles have a funnel-shape with a large opening that allows uniform filling of the etched feature 15 with conductive material, particularly when the conductive material is deposited by the line-of-sight deposition processes, such as sputter deposition.
The shape of the cross-sectional profile of the etched feature 15 can be quantified using different measurements, including for example, the L/V ratio and .theta. angle of the etched features. With reference to FIG. 1a, the L/V ratio provides a measure of the aperture and depth of the etched feature 15, where L is the length of the lateral overhang of the resist layer at the opening of the etched feature, and V is the vertical depth of the etched feature. The .theta. angle is a measure of the degree of "openness" of the etched feature 15, and is measured from the angle formed by the tangent to the upper sidewalls of the etched features 15 and the overhanging resist layer 14. The particular L/V ratio and .theta. angles that are desirable depend upon the desired cross-sectional profile of the etched feature 15, the dielectric material, and the type of deposition process that is subsequently used to deposit conductive material in the etched feature. Generally, an L/V ratio of about 1, and a .theta. angle of greater than about 90.degree. is desirable for features etched in dielectric layers such as, silicon dioxide deposited from TEOS (tetraethylorthosilane) or BPSG.
In conventional reactive ion etching (RIE) processes, the dielectric layer 10 is etched using a capacitive plasma formed from process gas comprising halogen-containing gases, such as for example, CF.sub.4 /O.sub.2, CF.sub.4 /NF.sub.3, NF.sub.3 /He, and CHF.sub.3 /CF.sub.4 /Ar. In RIE process, process gas is introduced into a chamber containing a substrate 11, and a capacitive plasma is generated from the process gas by applying an RF bias current to parallel and spaced apart process electrodes in the chamber. The resultant electric field generated between process electrodes has field lines perpendicular to the substrate, and the plasma ions accelerate in the direction of the electric field lines to energetically impinge upon and etch the dielectric layer 10 on the substrate 11.
Conventional RIE process typically provide "anisotropic" etching of the dielectric layer 10 resulting in etched features 15 that have straight and substantially vertical sidewalls 17, as shown in FIG. 1a. Anisotropic etching occurs because the energetic plasma ions, accelerated in the direction of the perpendicular electric field lines, provide high vertical etch rates through the dielectric layer 10 and low horizontal etching rates at the sidewalls 17 of the etched features 15. However, to control the shape of the etched feature, it is necessary to obtain a certain degree of horizontal etching at the sidewalls of the etched features, to provide a more "isotropic" etching process, that results in more open cross-sectional profiles. Thus, conventional RIE etching processes typically do not provide good control over the shape of the etched features 15, particularly for open-cup and wineglass shaped profiles.
It is known to modify RIE process steps to obtain a certain degree of anisotropic etching of the substrate 15. For example, U.S. Pat. No. 4,764,245, which is incorporated herein by reference, teaches a modified RIE plasma method for etching features with sloped sidewalls in oxide layers using (i) a first isotropic etching step that uses an etching gas containing free fluorine atoms such as CF.sub.4, and/or NF.sub.3 mixed with oxygen; and (ii) an anisotropic etching step that uses an etching gas containing free CF.sub.3 radicals and ions (such as CF.sub.4), mixed with NF.sub.3, and argon, helium, or nitrogen. The patent further teaches that during the isotropic etching step, the spacing of the electrodes in the chamber is increased to greater than 1 cm, and during the anisotropic step, the electrode spacing is reduced to less than 1 cm. Such multi-step RIE etching processes that use sequential isotropic and anisotropic etching steps are difficult to control, and often do not provide adequate control of the shape of the cross-sectional profile of the etched feature 15. Also, the multiple steps in the process reduce process throughput.
In another etching method, a microwave plasma or ECR source, is used to form the etching plasma by exciting the process gas using microwaves applied by a microwave applicator. Although microwave plasma processes provide superior isotropic etching characteristics; these processes often do not provide adequate control of the cross-sectional profile of the etched features. In particular, it has been observed that the profile of the etched features can vary depending upon the interaction of the microwave plasma with the different types of deposited dielectric layers, especially the silicon dioxide layers. For example, conventional microwave plasma processes for etching BPSG layers often result in etched features that have an excessively small LIV ratios and/or .theta. angles that are too large. In another example, microwave plasma processes used for etching silicon dioxide layers deposited from tetraethylorthosilane often result in etched features that have excessively large L/V ratios. Thus, conventional microwave plasma processes often fail to control the shape of the etched feature. Also, conventional microwave etching processes can also often result in etched features having a cusped cross-sectional profile, as for example shown in FIG. 1b. The cusped etched features typically have low LIV ratios of less than about 0.75, and often less than 0.5, and low .theta. angles of about 80.degree.. The low L/V ratios and .theta. angles do not allow uniform filling of the etched features 15, resulting in formation of overhangs at the corners and edges of the etched features. Upon further deposition, the overhangs coalesce to form voids and gaps within the deposited material, as schematically shown in FIG. 1c, resulting in poor electrical insulation, or electrical shorting.
Accordingly, there is a need for an etching process that provides control of the shape or cross-sectional profile of the features etched in the dielectric layer, to etch features having L/V ratios close to 1, and .theta. angles of less than about 90.degree.. It is further desirable for the etching process to provide high etching rates, good etching uniformity, and high etching selectivity ratio relative to photoresist.